Windows 10: Desktop computers not sufficient for Chief Architect Architectural Home Design Software

DANIEL L NEWHOUSE · May 26, 2022

The systems requirements are here https://www.chiefarchitect.com/products/sysreq.htmlAn RTX 3080 didn't used to be hard to come by.

:)

Cristian_25H · May 26, 2022

Computer Architect Jim Keller Joins AMD as Chief of Processor Group

AMD announced today that Jim Keller, 53, has joined the company as corporate vice president and chief architect of AMD's microprocessor cores, reporting to chief technology officer and senior vice president of technology and engineering Mark Papermaster. In this role, Keller will lead AMD's microprocessor core design efforts aligned with AMD's ambidextrous strategy with a focus on developing both high-performance and low-power processor cores that will be the foundation of AMD's future products.

"Jim is one of the most widely respected and sought-after innovators in the industry and a very strong addition to our engineering team," said Papermaster. "He has contributed to processing innovations that have delivered tremendous compute advances for millions of people all over the world, and we expect that his innovative spirit, low-power design expertise, creativity and drive for success will help us shape our future and fuel our growth."

Keller was most recently a director in the platform architecture group at Apple focusing on mobile products, where he architected several generations of mobile processors, including the chip families found in millions of Apple iPads, iPhones, iPods and Apple TVs. Prior to Apple, Keller was vice president of design for P.A. Semi, a fabless semiconductor design firm specializing in low-power mobile processors that was acquired by Apple in 2008. While there, he led the team responsible for building a powerful networking System on a Chip (SoC) and its integrated PowerPC processor. Keller previously worked at SiByte and Broadcom as chief architect for a line of scalable, MIPS-based network processors that supported 1Gig networking interfaces, PCI and other control functions. Before Broadcom, he spent several years at AMD, playing an instrumental role on the design team responsible for the groundbreaking AMD Athlon 64 and AMD Opteron 64 processors, which featured the world's first native x86-64 bit architecture.

Keller co-authored the widely adopted HyperTransport specification, as well as the innovative x86-64 processor instruction set, which is used around the world today in hundreds of millions of desktop, notebook and server systems. Jim was a corporate consulting engineer at DEC, and architected two generations of Alpha processors during his tenure there. He holds a Bachelor of Science degree in Electrical Engineering from Penn State University.

Brink · May 26, 2022

Trimble brings mixed reality to life for architecture and design

Last month, we showcased our aspiration to empower a new wave of creativity, and our goal to enable that through 3D and mixed reality for everyone. Today, we are thrilled to announce another important milestone in the Microsoft HoloLens and mixed reality journey.

This morning at Trimble Dimensions in Las Vegas, alongside Trimble CEO Steve Berglund and prominent architect Greg Lynn, I helped to introduce Trimble’s SketchUp Viewer, which is now available for purchase in the Windows Store. This marks the first extensible commercial HoloLens solution available in the Windows Store that any company in the Architecture, Engineering, Construction and Operations (AECO) industries can buy and use right away.

Today, SketchUp is widely used for 3D modeling and design by tens of millions of AECO professionals. SketchUp Viewer on HoloLens adopts mixed reality and extends the value and investment already made in 3D modeling with SketchUp. With this new solution, Trimble is taking 3D modeling as part of the design and construction process further and into what they call experiential review. SketchUp Viewer on HoloLens allows people to inhabit their designs in the most natural way possible – either as a holographic scale model on a tabletop, or through an immersive experience from within a digital building model. Viewing models in this way will enable designers to better understand the choices and tradeoffs in their projects, which can help shorten the cycle between design iterations. Perhaps most important, we believe experiential review will improve communication and collaboration across project stakeholders who participate in mixed reality experiences.

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Earlier this year, as part of the 2016 Venice Biennale architecture exhibition, Trimble and HoloLens partnered to enable architect Greg Lynn to use SketchUp Viewer to envision a drastic re-design of the Packard plant in Detroit that has been abandoned for half a century. SketchUp Viewer allowed Greg to cost-effectively visualize and navigate a holographic representation of the Packard Plant from the convenience of his work space in Venice Beach, California.

“Microsoft HoloLens and Trimble’s SketchUp Viewer have completely revolutionized the way I work,” says Lynn. “It actually changes the way you think about design and is an absolutely new way to experience architecture in a mode not previously possible.”

This is just one example of the truly innovative work we and Trimble have already seen using SketchUp Viewer on HoloLens, including from some of the world’s largest commercial AEC companies like, AECOM, CallisonRTKL, Gensler and Hensel Phelps as well as other pioneering design and construction firms. Through mixed reality on HoloLens, SketchUp Viewer brings complex architectural designs to life, providing an unmatched level of real-world scale, proportion and perspective. This technology enables higher quality decision making, collaboration, rapid iteration, incredible cost savings, and improved safety in just about every segment of architecture, engineering, construction and operations industries.

Architects, builders, designers, engineers and makers using SketchUp Viewer are the people who shape our world. We can’t wait to see how using SketchUp Viewer on HoloLens improves your design process.

Lorraine
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Source: Trimble brings mixed reality to life for architecture and design | Microsoft Devices Blog

Brink · May 26, 2022

Intel unveils new architectures for CPU, GPU, IPU and Client Computing

Architecture is alchemy of hardware and software. It blends the best transistors for a given engine, connects them through advanced packaging, integrates high-bandwidth, low-power caches, and equips them with high-capacity, high-bandwidth memories and low-latency scalable interconnects for hybrid computing clusters in a package, while also ensuring that all software accelerates seamlessly. Disclosing the architectural innovations that they have been working on for products that are imminent is something Intel’s architects look forward to each year at Intel Architecture Day, and this year’s event – our third – was the most exciting yet.

Today, we unveiled our biggest shifts in Intel® architectures in a generation. This includes the first in-depth look at Alder Lake, our first performance hybrid architecture with two new generations of x86 cores and the intelligent Intel® Thread Director workload scheduler; Sapphire Rapids, Intel’s new standard-setting data center architecture with our new Performance-core and various accelerator engines; our new discrete gaming graphics processing unit (GPU) architecture; new infrastructure processing units (IPUs); and Ponte Vecchio, our tour-de-force data center GPU architecture with Intel’s highest ever compute density.

These architectural breakthroughs set the stage for our next era of leadership products, starting soon with Alder Lake. The breakthroughs we disclosed today also demonstrate how architecture will satisfy the crushing demand for more compute performance as workloads from the desktop to the data center become larger, more complex and more diverse than ever.

More: Intel Architecture Day 2021 (Press Kit) | Intel Unveils Biggest Architectural Shifts in a Generation for CPUs, GPUs and IPUs (Architecture Day Fact Sheet) | Expanding Intel’s Foundry Partnerships: A Critical Piece of IDM 2.0 (Stuart Pann Editorial)

Our architects are working hard, combining Intel’s unique and rich selection of scalar, vector, matrix and spatial compute engines, to create hybrid computing architectures that deliver non-linear gains on our customers’ most demanding workloads.

You should visit our Newsroom press kit to watch the presentations, but let me walk you through the highlights:

Efficient-core: A highly scalable x86 microarchitecture for addressing compute requirements across the entire spectrum of our customer’s needs, from low-power mobile applications to many-core microservices. Compared with Skylake, Intel’s most prolific CPU microarchitecture, the Efficient-core delivers 40% more single-threaded performance at the same power, or the same performance while consuming less than 40% of the power.1 For throughput performance, four Efficient-cores deliver 80% more performance while still consuming less power than two Skylake cores running four threads or the same throughput performance while consuming 80% less power.

Performance-core: This x86 core is not only the highest performing CPU core Intel has ever built, but it also delivers a step function in CPU architecture performance that will drive the next decade of compute. It was designed as a wider, deeper and smarter architecture to expose more parallelism, increase execution parallelism, reduce latency and increase general purpose performance. It also helps support large data and large code footprint applications. Performance-core provides a Geomean improvement of about 19%, across a wide range of workloads over our current 11th Gen Intel® Core™ architecture (Cypress Cove core) at the same frequency.

Targeted for data center processors and for the evolving trends in machine learning, Performance-core brings dedicated hardware, including Intel's new Advanced Matrix Extensions (AMX), to perform matrix multiplication operations for an order of magnitude performance – a nearly 8x increase in artificial intelligence acceleration.1 This is architected for software ease of use, leveraging the x86 programing model.

Intel Thread Director: Intel’s unique approach to scheduling was developed to ensure Efficient-cores and Performance-cores work seamlessly together, dynamically and intelligently assigning workloads from the start and optimizing the system for maximum real-world performance and efficiency. With intelligence built directly into the core, Intel Thread Director works seamlessly with the operating system to place the right thread on the right core at the right time.

Alder Lake: Reinventing the multicore architecture, Alder Lake will be Intel’s first performance hybrid architecture with the new Intel Thread Director. This is Intel’s most intelligent client system-on-chip (SoC) architecture, featuring a combination of Efficient-cores and Performance-cores, scaling from ultra-mobile to desktop, and leading the industry transition with multiple industry leading I/O and memory. Products based on Alder Lake will begin shipping this year.

Xe HPG and Alchemist SoC: A new discrete graphics microarchitecture is designed to scale to enthusiast-class performance for gaming and creation workloads. The Xe HPG microarchitecture features a new Xe-core, a compute-focused programmable and scalable element, and full support for DirectX 12 Ultimate. New matrix engines inside the Xe-cores (referred to as Xe Matrix eXtensions, XMX) accelerate artificial intelligence workloads such as XeSS, a novel upscaling technology that enables high-performance and high-fidelity gaming. Xe HPG-based Alchemist SoCs (formerly code-named DG2) will be coming to market in the first quarter of 2022 under the new Intel® Arc™ brand.

Sapphire Rapids: Combining Intel’s Performance-cores with new accelerator engines, Sapphire Rapids sets the standard for next-generation data center processors. At the heart of Sapphire Rapids is a tiled, modular SoC architecture that delivers significant scalability while still maintaining the benefits of a monolithic CPU interface thanks to Intel’s EMIB multi-die interconnect packaging technology and advanced mesh architecture.

Infrastructure Processing Unit: Mount Evans is Intel's first dedicated ASIC-based IPU, along with a new FPGA-based IPU reference platform, Oak Springs Canyon. With an Intel IPU-based architecture, cloud service providers (CSPs) can maximize data center revenue by offloading infrastructure tasks from CPUs to IPUs. Offloading infrastructure tasks to the IPU allows CSPs to rent 100 percent of their server CPUs to customers.

Xe HPC, Ponte Vecchio: The most complex SoC Intel has ever built and a great example of our IDM 2.0 strategy come to life, Ponte Vecchio takes advantage of several advanced semiconductor processes, our revolutionary EMIB technology, and our Foveros 3D packaging. With this product, we are bringing to life our moon-shot project, the 100 billion-transistor device that delivers industry-leading FLOPs and compute density to accelerate artificial intelligence, high performance computing and advanced analytics workloads. At Architecture Day, we showed that our early Ponte Vecchio silicon is already demonstrating leadership performance, setting an industry-record in both inference and training throughput on a popular AI benchmark.1 Our A0 silicon is already providing greater than 45 TFLOPS FP32 throughput, greater than 5 TBps Memory Fabric bandwidth and greater than 2 TBps connectivity bandwidth. Ponte Vecchio, as with our Xe architectures, will be enabled by oneAPI, our open, standards-based, cross-architecture and cross-vendor unified software stack.

Looking back at just the past year, technology was at the heart of how we all communicated, worked, played and coped through the pandemic. Enormous computing power proved crucial. Looking ahead, we face a massive demand for compute – potentially a 1,000x need by 2025. That 1,000-times boost in four years is Moore’s Law to the power of five.

As our CEO, Pat Gelsinger, also an architect, stated at Architecture Day: “We face daunting compute challenges that can only be solved through revolutionary architectures and platforms … Our talented architects and engineers made possible all this technology magic.”

The world is counting on architects and engineers to solve the most difficult computational problems, to enrich people’s lives. Our strategy and execution are accelerating to meet these demands - at a torrid pace.

Raja M. Koduri is senior vice president and general manager of the Accelerated Computing Systems and Graphics Group at Intel Corporation.
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Source: Intel Advances Architecture for Data Center, HPC-AI and Client...

Windows 10: Desktop computers not sufficient for Chief Architect Architectural Home Design Software

Desktop computers not sufficient for Chief Architect Architectural Home Design Software

Desktop computers not sufficient for Chief Architect Architectural Home Design Software

Desktop computers not sufficient for Chief Architect Architectural Home Design Software

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Trimble brings mixed reality to life for architecture and design