Windows 10: PCI-SIG announces new PCI Express 5.0 specification

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• 5.0 Out of 5 Stars: PCI-SIG(R) Member Companies Announce Support for the PCI Express(R) 5.0 Specification | PCI-SIG
• PCI-SIG(R) Achieves 32GT/s with New PCI Express(R) 5.0 Specification | Business Wire

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PCI-SIG Finalizes PCI-Express 3.0 Specifications

The PCI-SIG finalized the specifications of PCI-Express 3.0 bus, the latest version of PCI. Like PCI-Express 1.x and PCI-Express 2.x, PCI-E 3.0 is designed to be backwards-compatible with devices that use older versions of the bus. Keeping up with the major version trend, PCI-E 3.0 doubles the theoretical bandwidth. PCI-Express 3.0 can push 1 GB/s per lane, per direction, double that of PCI-E 2.0. A PCI-Express 3.0 x16 slot would hence have its cumulative bandwidth at 32 GB/s.

Apart from pure bandwidth increases, PCI-Express also uses the new 128b/130b data encoding scheme, which reduces protocol overhead significantly, allowing near-100% utilization of available bandwidth. To put this into perspective, PCI-Express 2.0 had a data-rate of 5 GT/s, but with its overhead, could only effectively transfer 4 GT/s. The new scheme allows utilization of all 8 GT/s of the bandwidth PCI-Express 3.0 has, resulting in a data-rate of 1 GB/s per lane, per direction. The PCI-E specification document is available to PCI-SIG members. It is expected that the first PCI-Express 3.0 compliant devices will come to be in 2011.

 

NVIDIA on PCI-SIG Integrator List

NVidia reports that they are the first GPU manufacturer to pass the PCI-SIG Workshop tests and thus make it onto the PCI-SIG Integrators List.

PCI-SIG is the Special Interest Group that owns and manages PCI specifications as open industry standards. The organization defines and implements new industry standard I/O (Input/Output) specifications as the industry's local I/O needs evolve.


SANTA CLARA, CA—AUGUST 23, 2004—NVIDIA Corporation (Nasdaq: NVDA), a worldwide leader in visual processing solutions, today announced that PCI-SIG*, the Special Interest Group responsible for Conventional PCI, PCI-X* and PCI Express* industry-standard I/O technologies, has indicated NVIDIA PCI Express technology-based products have passed the Workshop compliance test suite by adding the products to the PCI-SIG Integrators List. NVIDIA is the only graphics processing unit (GPU) manufacturer on the PCI-SIG Integrators List, and has a full range of NVIDIA products listed, including GPUs designed for workstations, desktops, and notebook computers. To be placed on the PCI-SIG Integrators List, products must undergo a significant set of interoperability and compliance testing requirements, and pass a detailed ‘Compliance Checklist’.

Tony Pierce, PCI-SIG Chairman stated, "NVIDIA's contribution to the PCI Express standard is evident in the breadth of their product offerings that passed our compliance testing. PCI-SIG congratulates NVIDIA for being a part of the first group of member companies to be listed in our Integrators List for their PCI Express technology products. We look forward to NVIDIA’s continuous support to invigorate the PC and workstation markets through the additional value that PCI Express technology has to offer.”

"The fact that NVIDIA brought such a broad selection of PCI Express products to market quickly and is the only major GPU manufacturer on the PCI-SIG Integrators List is a testament to our world-class engineering and design strategy," commented Dan Vivoli, executive vice president of marketing at NVIDIA.

 

PCI SIG Releases PCI-Express Gen 4.0 Specifications

The Peripheral Component Interconnect (PCI) special interest group (SIG) published the first official specification (version 1.0) of PCI-Express gen 4.0 bus. The specification's previous draft 0.9 was under technical review by members of the SIG. The new generation PCIe comes with double the bandwidth of PCI-Express gen 3.0, reduced latency, lane margining, and I/O virtualization capabilities. With the specification published, one can expect end-user products implementing it. PCI SIG has now turned its attention to the even newer PCI-Express gen 5.0 specification, which will be close to ready by mid-2019.

PCI-Express gen 4.0 comes with 16 GT/s bandwidth per-lane, per-direction, which is double that of gen 3.0. An M.2 NVMe drive implementing it, for example, will have 64 Gbps of interface bandwidth at its disposal. The SIG has also been steered toward lowering the latencies of the interconnect as HPC hardware designers are turning toward alternatives such as NVLink and InfinityFabric, not primarily for the bandwidth, but the lower latency. Lane margining is a new feature that allows hardware to maintain a uniform physical layer signal clarity across multiple PCIe devices connected to a common root complex. This is particularly important when you have multiple pieces of mission-critical hardware (such as RAID HBAs or HPC accelerators), and require uniform performance across them. The new specification also adds new I/O virtualization features that should prove useful in HPC and cloud computing.